Let us take as an example one of those ADS9850 DDS boards available on EvilBay. These come equipped with a 125 MHz crystal oscillator that will likely be within 10-20 ppm or so, but let us assume that it is exactly 125 MHz.
Other than the 125 MHz clock and some output filtering, the AD9850 DDS chip has nearly everything else that one would need to generate an output from DC to around 60 MHz - the precise limit depending on filtering - and its frequency is set using a 32 bit "tuning word". The combination of the 125 MHz clock and the 32 bit tuning word means that our frequency resolution is:
- 125,000,000 / (232) = 125,000,000 / 4,294,967,296 = 0.02910383045673370361328125... Hz per step - approximately.
The quick answer to this is to pick a clock frequency that is an exact "power of two" Hz, and the closest 2n multiple to 125 MHz is 227 or 134.217728... MHz - slightly beyond the ratings of the AD9850, but it is likely to work. (Depending on the high frequency requirements, half of this frequency - 226 Hz, or 65.108864 MHz might be used instead: Other frequencies that are 2n divided by an integer such as 2n/10 are usable, too as an example.)
What does this change in clock frequency gain for us, then?
- 227 / 232 = 0.03125 Hz per step, which is exactly 1/32nd Hz.
(Where does one get a 134.217728 or 65.108864 MHz oscillator? This would likely require a custom-made crystal/oscillator or it could be produced using another synthesizer such as an SI5351A that, itself, uses a VCXO as its reference.)
It would make sense that if you actually needed to be able to set your frequency to exact 1 Hz multiples that you would also need to precisely control the reference frequency as well - likely with a 10 MHz precise reference from a GPS Disciplined Oscillator (GPSDO), a Rubium frequency reference or something similar. Unfortunately, 227Hz is an awkward number that doesn't easily relate to a 10 MHz reference.
The most obvious way to do this is to use a second DDS generator board (they are cheap enough!) clocked from the same 227Hz source with its output to exactly 10 MHz using a frequency word of 320,000,000d, comparing it to the local standard and applying frequency corrections to (e.g. shift slightly) the actual frequency of the "227Hz" oscillator.
There is a less-obvious way to do this as well, so here is an example using 224 Hz - which is 16.777216 MHz:
- Take the 10 MHz output and divide it by 625 to yield 16.000 kHz
- Multiply the 16.000 kHz by 32 to yield 512.000 kHz
- Divide 512 kHz by 125 to yield 4096 Hz
- Divide any 2n Hz frequency down to 4096 Hz as a basis of comparison. For 224 Hz we would divide-by 4096 using a binary divider.
Why would anyone use this second method? Back in the 1980s I built a DDS synthesizer that used a 224 Hz reference (16.777216 MHz) that used a 24-bit tuning word to provide precise 1 Hz steps, but I also needed to lock that same synthesizer to a high-quality 10 MHz TCXO. While it would have been possible to have built another synthesizer, a 1980s solution to this problem meant that an entire synthesizer circuit (or most of it, anyway) consisting of more than a dozen chips - some of them rather expensive - would have have to be replicated to do this one thing.
This seemingly convoluted solution required required only 6 inexpensive chips - a combination of 74HC (or LS-TTL) and some 4000 series CMOS devices. For example:
- Dividing the 10 MHz reference by 625: A 74HC40103 wired as a divide-by-125 followed by a 4017 counter wired as a divide-by-5 to yield 16 kHz.
- The multiplication of 16 kHz by 32 to 512 kHz: A 4046 PLL and a 4040 counter to form a synthesizer.
- Division of 512 kHz to 4096 Hz: Another 40103 wired as a divide-by-125.
- Division of 16.777216 MHz down to 4096 Hz: A 74HC4040 counter dividing by 4096.
A comment about using the 4046 PLL chip:
It's worth noting that because the 4096Hz output from the divide-by-125 from the 512kHz source is a pulse rather than a square wave so it is not possible to use the "XOR" phase detector (Phase detector 1) of the 40406, but rather the flip-flip detector (Phase detector 2). The "problem" with the flip-flop detector is that when the two frequencies are close, instead of having a constant train of pulses being output that are either at the reference frequency or twice the reference frequency, one will get occasional, brief pulses as the output of one of the flip-flops occasionally drops out of its high-impedance mode.
The problem with is that these occur (more or less) randomly and comparatively rarely, meaning that they they are at a rather low frequency and can get through the loop filter, causing extra jitter on the locked frequency - the 16.777216 MHz oscillator in this case. The "fix" for this is to slightly bias the output of the phase comparator toward V+ or ground with a high-value resistor (100k-4.7 Meg, depending on the application) which will "pull" the output constantly toward one rail, forcing the loop to be corrected constantly meaning that instead of the occasional, narrow pulse, there will always be a string of pulses at a "high-ish" frequency that can be removed by the loop filter. With the rather low "loop gain" of this VXCO configuration, "jitter" caused by the multiplication synthesis and divisions really doesn't show up in the 224 Hz crystal oscillator being locked.
Even though the 4046 CMOS with its built-in oscillator and phase/frequency detector is a bit "jittery", remember that this is being applied with a slow loop filter to a VCXO circuit with very low overall loop gain so this jitter pretty much averages out.
(If our 134-ish MHz clock were produced using an SI5351A synthesizer, the PLL corrections in this scheme would be applied to its clock, which typically operates at around 27 MHz.)
Nowadays, with GPSDOs and second-hand rubidium references being affordable, the accuracy and stability can be improved by several orders of magnitude beyond that of the TCXO that I used those many years ago.
Having said all of this the question must be asked: Is any of this still useful?
You never know!
This page stolen from ka7oei.blogspot.com